As it is well known in this technical field, for applications relating to non-linear decoding channels for digital transmission, electronic devices capable of implementing a scale network comprising LC non-linear elements would be needed. In fact, research carried out by the Applicant indicates that a non-linear channel would provide improved performance with respect to a standard transmission channel.
For example, the here-attached FIG. 1 schematically illustrates the structure of a scale network comprising n LC non-linear elements cascade connected together.
The network of FIG. 1 is essentially a quadrupole having a pair of input terminals to which a voltage potential Vo is applied, and having a pair of output terminals to which a resistive load Rt is connected.
All the pairs of LC non-linear elements, which is L1, C1; . . . , Li, Ci, . . . , Ln, Cn, have the same value. In other words, all the L components are identical with one another, as are the C components.
In particular, the non-linear equations that the network of FIG. 1 would be expected to implement are the following:
                              Equation          ⁢                                          ⁢                      (            1            )                          ⁢                                  ⁢                  C          =                                    C              0                                      1              +                                                (                                                            V                      C                                                              V                      0                                                        )                                2                                                                        (        1        )            where, C0 and V0 are constants; and
                              Equation          ⁢                                          ⁢                      (            2            )                          ⁢                                  ⁢                  L          =                                    L              0                                      1              +                                                (                                                            I                      L                                                              I                      0                                                        )                                2                                                                        (        2        )            where, L0 and I0 are constants.
FIG. 2 shows schematically a possible circuit embodiment based on the use of a derivator.
A bipolar transistor differential cell BJT receives a bias current I1 on a first circuit branch, and it is connected to ground by a current generator I. A potential equal to Vc lies across the emitter terminals of the transistor pair.
A transistor output stage, being supplied by a current Ic, is connected to said first circuit branch and has an output terminal connected to ground through the parallel of a capacitance and a current generator.
This embodiment is based on the following approximate equation:
                              Equation          ⁢                                          ⁢                                                    (                3                )                            ⁢                                                          [                              1                +                                                      (                                                                  V                        C                                                                    V                        0                                                              )                                    2                                            ]                                      -              1                                      ≅                  hyp          ⁢                                          ⁢          sec          ⁢                                          ⁢                                    h              2                        ⁡                          (                                                V                  C                                                  V                  0                                            )                                                          (        3        )            
The exponential voltage-current characteristic of the transistor pair BJT of the differential cell allows the desired non-linear equations to be synthesized where the substitution indicated in Equation (3) is carried into effect.
However, the dynamic performance of this hypothetical embodiment based on the use of a derivator would be inadequate to meet the requirements of the above application field.
If taking into consideration the non-linear capacitance alone, a possible embodiment of the network of FIG. 1 could be provided through the use of an integrator instead of a derivator. In this way, the superior dynamic characteristics of the integrator with respect to the derivator could be exploited.
An embodiment based on an integrator should implement the following operations:
                              Equation          ⁢                                          ⁢                      (            4            )                          ⁢                                  ⁢                              I            C                    =                                                                                          C                    0                                                        1                    +                                                                  (                                                                              V                            C                                                                                V                            0                                                                          )                                            2                                                                      ⁢                                                      ∂                                          V                      C                                                                            ∂                    t                                                              ⇒                                                1                                      C                    0                                                  ⁢                                  ∫                                                                                    I                        C                                            ⁡                                              [                                                  1                          +                                                                                    (                                                                                                V                                  C                                                                                                  V                                  0                                                                                            )                                                        2                                                                          ]                                                              ⁢                                          ⅆ                      t                                                                                            =                          V              C                                                          (        4        )            from which it is evinced that two multipliers would be needed.
A circuit device realized according to Equation (3) would be highly complicated. Moreover this would be even worse since the scale network of FIG. 1 contains n LC pairs and, when the number n is greater than 10, as required in most applications, the complexity of the circuit embodiment would limit high-frequency performance.